Content addressable memories (CAMs) are known. In CAMs, data is selected based on contents, rather than physical location. This function is useful for many applications, especially when performing a look-up for the purposes of mapping. This operation is required in many telecommunications (telecom) functions, including Asynchronous Transfer Mode (ATM) address translation.
Often, system storage requirements exceed the number of entries stored on a single CAM array. Multiple CAM arrays, possibly on multiple chips, are then required, and it is necessary to cascade the multiple CAM arrays such that they may be searched as a single entity. An appropriate "user-friendly" cascading capability enables the same CAM array to be used in a range of systems with different capacity requirements, and allows for easy expandability and scalability, as well.
U.S. Pat. No. 5,568,416 granted to K. Kawana et al on Oct. 22, 1996 discloses an associative memory in which multiple CAM chips are cascaded by propagating a result address and status through all chips in the cascade. Each chip contains a status register for itself, and another for all upstream chips. It also discloses means of identifying the last device in the cascade, and separate storage areas for common and unique data entries.